View ADM2483_561314.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Half-Duplex iCoupler(R) Isolated RS-485 Transceiver ADM2483
FEATURES
RS-485 transceiver with electrical data isolation Complies with ANSI TIA/EIA RS-485-A-1998 and ISO 8482:1987(E) 500 kbps data rate Slew rate-limited driver outputs Low power operation: 2.5 mA max Suitable for 5 V or 3 V operation (VDD1) High common-mode transient immunity: >25 kV/s True fail-safe receiver inputs Glitch-free power-up/-down protection 256 nodes on bus Thermal shutdown protection Safety and regulatory approvals: UL recognition: 2500 VRMS for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN EN 60747-5-2 (VDE 0884 Rev. 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 VIORM = 560 V peak Operating temperature range: -40C to +85C
FUNCTIONAL BLOCK DIAGRAM
VDD1 VDD2
TxD POWER_VALID RxD RE GND1
GALVANIC ISOLATION
DE
ADM2483
A B
04736-001
GND2
Figure 1.
APPLICATIONS
Low power RS-485/RS-422 networks Isolated interfaces Building control networks Multipoint data transmission systems
GENERAL DESCRIPTION
The ADM2483 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on balanced, multipoint bus transmission lines. It complies with ANSI TIA/EIA RS-485-A and ISO 8482:1987(E). Using Analog Devices' iCoupler(R) technology, the ADM2483 combines a 3-channel isolator, a 3-state differential line driver, and a differential input receiver into a single package. The logic side of the device is powered with either a 5 V or 3 V supply, while the bus side uses a 5 V supply only. The ADM2483 is slew-limited to reduce reflections with improperly terminated transmission lines. The controlled slew rate limits the data rate to 500 kbps. The device's input impedance is 96 k, allowing up to 256 transceivers on the bus. Its driver has an active-high enable. The driver differential
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
outputs and receiver differential inputs are connected internally to form a differential I/O port. When the driver is disabled or when VDD1 or VDD2 = 0, this imposes minimal loading on the bus. An active-high receiver disable, which causes the receive output to enter a high impedance state, is provided as well. The receiver inputs have a true fail-safe feature that ensures a logic-high receiver output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and at the point when communication ends. Current limiting and thermal shutdown features protect against output short circuits and bus contention situations that might cause excessive power dissipation. The part is fully specified over the industrial temperature range and is available in a 16-lead wide body SOIC package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADM2483 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Specifications....................................................................... 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Package Characteristics ............................................................... 6 Regulatory Information............................................................... 6 Insulation and Safety-Related Specifications............................ 6 VDE 0884 Insulation Characteristics, ....................................... 7 Pin Configurations and Function Descriptions ........................... 8 Test Circuits....................................................................................... 9 Switching Characteristics .............................................................. 10 Typical Performance Characteristics ........................................... 11 Circuit Description......................................................................... 14 Electrical Isolation...................................................................... 14 Truth Tables................................................................................. 15 Power-Up/Power-Down Characteristics................................. 15 Thermal Shutdown .................................................................... 15 True Fail-Safe Receiver Inputs .................................................. 15 Magnetic Field Immunity.......................................................... 15 Applications Information .............................................................. 17 Power_Valid Input ..................................................................... 17 Isolated Power Supply Circuit .................................................. 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
10-04--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADM2483 SPECIFICATIONS
2.7 VDD1 5.5 V, 4.75 V VDD2 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 1.
Parameter DRIVER Differential Outputs: Differential Output Voltage, VOD Min Typ Max Unit Test Conditions/Comments
2.0 1.5 1.5 |VOD| for Complementary Output States Common-Mode Output Voltage, VOC |VOC| for Complementary Output States Output Short-Circuit Current, VOUT = High Output Short-Circuit Current, VOUT = Low Logic Inputs: Input High Voltage Input Low Voltage CMOS Logic Input Current (TxD, DE, RE, PV) RECEIVER Differential Inputs: Differential Input Threshold Voltage, VTH Input Hysteresis Input Resistance (A, B) Input Current (A, B) RxD Logic Output: Output High Voltage
5 5 5 5 0.2 3 0.2 +250 +250
V V V V V V V mA mA V V A
-250 -250 0.7 VDD1 -10 +0.01
R = , Figure 3 R = 50 (RS-422), Figure 3 R = 27 (RS-485), Figure 3 VTST = -7 V to 12 V, VDD1 4.75, Figure 4 R = 27 or 50 , Figure 3 R = 27 or 50 , Figure 3 R = 27 or 50 , Figure 3 -7 V VOUT + 12 V -7 V VOUT + 12 V TxD, DE, RE, PV TxD, DE, RE, PV TxD, DE, RE, PV = VDD1 or 0 V
0.25 VDD1 +10
-200 96
-125 20 150
-30
0.125 -0.1 VDD1 -0.1 VDD1 -0.4
mV mV k mA mA V V
-7 V VCM +12 V -7 V VCM +12 V -7 V VCM +12 V VIN = +12 V VIN = -7 V IOUT = 20 A, VA - VB = 0.2 V IOUT = 4 mA, VA - VB = 0.2 V IOUT = -20 A, VA - VB = -0.2 V IOUT = -4 mA, VA - VB = -0.2 V VOUT = GND or VCC 0.4 V VOUT 2.4 V 4.5 V VDD1 5.5 V, Outputs Unloaded, RE = 0 V 2.7 V VDD1 3.3 V, Outputs Unloaded, RE =0V Outputs Unloaded, DE = 5 V Outputs Unloaded, DE = 0 V T x D = VDD1 or 0 V, VCM = 1 kV, Transient Magnitude = 800 V
VDD1 -0.2 0.1 0.4 85 1 2.5 1.3
Output Low Voltage Output Short-Circuit Current Three-State Output Leakage Current POWER SUPPLY CURRENT Logic Side 7
V V mA A mA mA mA mA kV/s
Bus Side COMMON-MODE TRANSIENT IMMUNITY1 25
2.0 1.7
1
Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. 0 | Page 3 of 20
ADM2483 TIMING SPECIFICATIONS
2.7 VDD1 5.5 V, 4.75 V VDD2 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 2.
Parameter DRIVER Maximum Data Rate Propagation Delay, tPLH, tPHL Skew, tSKEW Rise/Fall Time, tR, tF Enable Time Disable Time RECEIVER Propagation Delay, tPLH, tPHL Differential Skew, tSKEW Enable Time Disable Time POWER VALID INPUT Enable Time Disable Time Min 500 250 200 Typ Max Units kbps ns ns ns ns ns ns ns ns ns s s Test Conditions/Comments
620 40 600 1050 1050 1050 250 70 70 2 5
RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 5 and Figure 9 RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 5 and Figure 9 RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 5 and Figure 9 RL = 500 , CL = 100 pF, Figure 6 and Figure 11 RL = 500 , CL = 15 pF, Figure 6 and Figure 11 CL = 15 pF, Figure 7 and Figure 10 CL = 15 pF, Figure 7 and Figure 10 RL = 1 k, CL = 15 pF, Figure 8 and Figure 12 RL = 1 k, CL = 15 pF, Figure 8 and Figure 12
400 25 40 1 3
Rev. 0 | Page 4 of 20
ADM2483 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. All voltages are relative to their respective ground. Table 3.
Parameter VDD1 VDD2 Digital Input Voltage (DE, RE, T x D) Digital Output Voltage RxD Driver Output/Receiver Input Voltage Operating Temperature Range Storage Temperature Range Average Output Current per Pin JA Thermal Impedance Lead Temperature Soldering (10 s) Vapor Phase (60 s) Infrared (15 s) Rating -0.5 V to +7 V -0.5 V to +6 V -0.5 V to VDD1 +0.5 V -0.5 V to VDD1 +0.5 V -9 V to +14 V -40C to +85C -55C to +150C -35 mA to +35 mA 73C/W 260C 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 20
ADM2483
PACKAGE CHARACTERISTICS
Table 4.
Parameter Resistance (Input - Output)1 Capacitance (Input - Output)1 Input Capacitance2 Input IC Junction-to-Case Thermal Resistance Output IC Junction-to-Case Thermal Resistance Symbol RI-O CI-O CI JCI JCO Min Typ 101, 2 3 4 33 28 Max Unit pF pF C/W C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside Thermocouple located at center of package underside
1 2
Device considered a two-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together. Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADM2483 has been approved by the following organizations: Table 5.
UL1 Recognized under 1577 component recognition program CSA Approved under CSA Component Acceptance Notice #5A VDE2 Approved according to DIN EN 60747-5-2 (VDE 0884 Rev. 2): 2002-04 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 File 2471900-4880-0001
File E214100
File 205078
1 2
In accordance with UL1577, each ADM2483 is proof-tested by applying an insulation test voltage 3000 Vrms for 1 s (current leakage detection limit = 5 A). In accordance with VDE 0884, each ADM2483 is proof-tested by applying an insulation test voltage 1050 VPEAK for 1 s (partial discharge detection limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 2500 8.40 min 8.1 min 0.017 min >175 IIIa Unit VRMS mm mm mm V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (Table 1 in DIN VDE 0110,1/89)
CTI
Rev. 0 | Page 6 of 20
ADM2483
VDE 0884 INSULATION CHARACTERISTICS1, 2
Table 7.
Description Installation classification per DIN VDE 0110 for rated mains voltage 150 Vrms 300 Vrms 400 Vrms Climatic classification Pollution degree (Table 1 in DIN VDE 0110) Maximum working insulation voltage Input to output test voltage, method b1 VIORM x 1.875 = VPR, 100% production tested tm = 1s, partial discharge <5 pC Input to output test voltage, method a (After environmental tests, subgroup 1) VIORM x 1.6 = VPR, tm = 60 s, partial discharge <5 pC (After input and/or safety test, subgroup 2/3) VIORM x 1.2 = VPR, tm = 60 s, partial discharge <5 pC Highest allowable overvoltage (Transient overvoltage, tTR = 10 s) Safety-limiting values (Maximum value allowed in the event of a failure. See thermal derating curve, Figure 24.) Case temperature Input current Output current Insulation resistance at TS, VIO = 500 V Symbol Characteristic I to IV I to III I to II 40/85/21 2 560 1050 Unit
VIORM VPR
VPEAK VPEAK
896 VPR VTR 672 4000
VPEAK VPEAK VPEAK
TS IS, INPUT IS,OUTPUT RS
150 265 335 >109
C mA mA
1
2
Suitable for basic electrical isolation only within this safety limit data. Maintenance of this safety data shall be ensured by means of protective circuits. An asterisk (*) on the physical package denotes VDE 0884 approval for 560 V peak working voltage.
Rev. 0 | Page 7 of 20
ADM2483 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1 GND1* 2 RxD 3 RE 4
16 VDD2 15 GND2*
13 B TOP VIEW DE 5 (Not to Scale) 12 A
ADM2483
14 NC
TxD 6 PV 7 GND1* 8
11 NC 10 NC 9
GND2*
NC = NO CONNECT * PINS 2 AND 8 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR GND1. PINS 9 AND 15 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR GND2.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. 1 2, 8 3 4 5 6 7 9, 15 10, 14 12 13 16 Mnemonic VDD1 GND1 RxD RE DE TxD PV GND2 NC A B VDD2 Description Power Supply (Logic Side). Ground (Logic Side). Receiver Output Data. This output is high when (A - B) > 200 mV, and low when (A - B) < -200 mV. There is tristate output when the receiver is disabled, i.e., when RE is driven high. Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver, and driving it high disables the receiver. Driver Enable Input. Driving this input high enables the driver, and driving it low disables the driver. Transmit Data Input. Data to be transmitted by the driver is applied to this input. Power Valid. Used during power-up and power-down. See the Applications Information section. Ground (Bus Side). No Connect. Noninverting Driver Output/Receiver Input. When the driver is disabled, or VDD1 or VDD2 is powered down, Pin A is put in a high impedance state to avoid overloading the bus. Inverting Driver Output/Receiver Input. Power Supply (Bus Side).
Rev. 0 | Page 8 of 20
04736-002
ADM2483 TEST CIRCUITS
VCC
R VOD
04736-003
A 0V OR 3V
DE DE IN
RL S1
S2
CL VOUT
04736-006
R
VOC
B
Figure 3. Driver Voltage Measurement
Figure 6. Driver Enable/Disable
375
A
VTST
04736-004
CL
375
Figure 4. Driver Voltage Measurement
Figure 7. Receiver Propagation Delay
+1.5V
A RLDIFF B
CL1
-1.5V
04736-005
S1
RE
RL
S2
04736-007
VOD3
60
B
RE
VOUT
VCC
CL2
CL VOUT
RE IN
Figure 5. Driver Propagation Delay
Figure 8. Receiver Enable/Disable
Rev. 0 | Page 9 of 20
04736-008
ADM2483 SWITCHING CHARACTERISTICS
VDD1 0.5VDD1 0V B VO
A, B 0.7VDD1
0.5VDD1
DE
0.5VDD1
0.5VDD1 0.3VDD1
tPLH
1/2VO
tPHL
tZL
2.3V
tLZ
A
VOL +0.5V VOL
tSKEW = |tPLH - tPHL|
VO 0V 10% POINT -VO 10% POINT
04736-009
tZH
90% POINT
A, B 2.3V
tHZ
VOH
04736-011 04736-012
90% POINT
VOH -0.5V 0V
tR
tF
Figure 9. Driver Propagation Delay, Rise/Fall Timing
Figure 11. Driver Enable/Disable Timing
0.7VDD1
A-B
0V
0V
RE
0.5VDD1
0.5VDD1 0.3VDD1
tZL
tLZ
tPLH
tPHL
VOH
RxD 1.5V O/P LOW VOL +0.5V VOL
RxD
1.5V
04736-010
tSKEW = |tPLH - tPHL|
1.5V VOL
tZH
O/P HIGH RxD 1.5V 0V
tHZ
VOH VOH -0.5V
Figure 10. Receiver Propagation Delay
Figure 12. Receiver Enable/Disable Timing
Rev. 0 | Page 10 of 20
ADM2483 TYPICAL PERFORMANCE CHARACTERISTICS
1.6 IDD1_RCVR_ENABLE @ 5.5V 1.4
0.32
0.30
1.2
OUTPUT VOLTAGE (V)
0.28
1.0
(mA)
0.8 IDD2_DE_ENABLE @ 5.5V 0.6 0.4
04736-038
0.26
0.24
0.22
04736-031
0.2 0 -40 +25 TEMPERATURE (C) +85
0.20 -40
-25
-10
5 20 35 TEMPERATURE (C)
50
65
80
Figure 13. Unloaded Supply Current vs. Temperature
120
Figure 16. Receiver Output Low Voltage vs. Temperature, I=-4mA
4.78
100
4.76
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
80
4.74
60
4.72
40
4.70
20
04736-014
4.68
04736-032
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5 5.0
4.66 -40
-25
-10
5 20 35 TEMPERATURE (C)
50
65
80
Figure 14. Output Current vs. Driver Output Low Voltage
-10
Figure 17. Receiver Output High Voltage vs. Temperature, I = 4 mA
90 80
DRIVER OUTPUT CURRENT (mA)
04736-015
OUTPUT CURRENT (mA)
-30
70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 DIFFERENTIAL OUTPUT VOLTAGE (V) 4.5 5.0
04736-013
-50
-70
-90
-110 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5 5.0
Figure 15. Output Current vs. Driver Output High Voltage
Figure 18. Driver Output Current vs. Differential Output Voltage
Rev. 0 | Page 11 of 20
ADM2483
460
tP_BLH @
VDD1 = VDD2 = 5.0V
1
440
tP_AHL @
VDD1 = VDD2 = 5.0V 420
TIME (ns)
400
tP_BHL @
VDD1 = VDD2 = 5.0V 380
3
tP_ALH @ VDD1 = VDD2 = 5.0V
360
04736-034
04736-022
4
340 -40 +25 TEMPERATURE (C) +85
CH1 5.00V CH3 2.00V
CH2 2.00V CH4 5.00V
M2.00ns A CH1 T 2.41200s
2.50V
Figure 19. Driver Propagation Delay vs. Temperature
800 700 600 500 RCVR PROP LH/VDD1 = VDD2 = 5.0V
Figure 21. Driver/Receiver Propagation Delay High to Low
RCVR PROP HL/VDD1 = VDD2 = 5.0V
1
TIME (ns)
400 300 200
04736-035
04736-023
100 0 -40 +25 TEMPERATURE (C) +85
3 4
CH1 5.00V CH3 1.00V
CH2 1.00V CH4 5.00V
M2.00ns A CH1 T 492.000ns
2.50V
Figure 20. Receiver Propagation Delay vs. Temperature
Figure 22. Driver/Receiver Propagation Delay Low to High
Rev. 0 | Page 12 of 20
ADM2483
350
35
300
30
SAFETY-LIMITING CURRENT (mA)
250 BUS SIDE 200 150 LOGIC SIDE 100
OUTPUT CURRENT (mA)
25
20 15
10 5
04736-024
0
0
50
100 150 CASE TEMPERATURE (C)
200
0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 OUTPUT VOLTAGE (V) 2.00 2.25
Figure 23. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per VDE 0884
0
Figure 25. Output Current vs. Receiver Output Low Voltage
-5
OUTPUT CURRENT (mA)
-10
-15
-20
-25
04736-036
-30 3.0
3.2
3.4
3.6 3.8 4.0 4.2 4.4 OUTPUT VOLTAGE (V)
4.6
4.8
5.0
Figure 24. Output Current vs. Receiver Output High Voltage
Rev. 0 | Page 13 of 20
04736-037
50
ADM2483 CIRCUIT DESCRIPTION
ELECTRICAL ISOLATION
In the ADM2483, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 19). Driver input and data enable signals, applied to the TxD and DE pins respectively, and referenced to logic ground (GND1), are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (GND2). Similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground.
iCoupler Technology
The digital signals are transmitted across the isolation barrier using iCoupler technology. This technique uses chip scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted.
VDD1
VDD2
ISOLATION BARRIER A TxD ENCODE DECODE D B
DE
ENCODE
DECODE
RxD RE
ENCODE
DECODE
R
DIGITAL ISOLATION GND1
TRANSCEIVER GND2
Figure 26. ADM2483 Digital Isolation and Transceiver Sections
Rev. 0 | Page 14 of 20
04736-025
ADM2483
TRUTH TABLES
The following truth tables use these abbreviations:
Letter H L X Z NC Description High Level Low Level Irrelevant High Impedance (Off) Disconnected
THERMAL SHUTDOWN
The ADM2483 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150C is reached. As the device cools, the drivers are reenabled at a temperature of 140C.
Outputs B L H Z Z Z Z
Table 9.Transmitting
Supply Status VDD1 VDD2 On On On On On On On Off Off On Off Off DE H H L X X X Inputs TxD H L X X X X A H L Z Z Z Z
TRUE FAIL-SAFE RECEIVER INPUTS
The receiver inputs have a true fail-safe feature, which ensures that the receiver output is high when the inputs are open or shorted. During line-idle conditions, when no driver on the bus is enabled, the voltage across a terminating resistance at the receiver input will decay to 0 V. With traditional transceivers, receiver input thresholds specified between -200 mV and +200 mV mean that external bias resistors are required on A and B pins to ensure that the receiver outputs are in a known state. The true fail-safe receiver input feature eliminates the need for bias resistors by specifying the receiver input threshold between -30 mV and -200 mV. The guaranteed negative threshold means that when the voltage between A and B decays to 0 V, the receiver output is guaranteed to be high.
Table 10. Receiving
Supply Status VDD1 On On On On On On Off Off VDD2 On On On On On Off On Off Inputs A - B (V) >-0.03 <-0.2 -0.2 < A - B < -0.03 Inputs Open X X X X Outputs RxD H L Indeterminate H Z H H L
RE
L or NC L or NC L or NC L or NC H L or NC L or NC L or NC
MAGNETIC FIELD IMMUNITY
The ADM2483 is immune to external magnetic fields. Its magnetic field immunity is set when induced voltage in the transformer's receiving coil is large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. Because it represents the most susceptible mode of operation, the ADM2483's 3 V operating condition is examined as an example. The pulses at the transformer output are greater than 1.0 V in amplitude. The decoder has sensing thresholds at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by
POWER-UP/POWER-DOWN CHARACTERISTICS
The power-up/-down characteristics of the ADM2483 are in accordance with the supply thresholds shown in Table 11. Upon power-up, the ADM2483 output signals (A, B, and RxD) reach their correct state once both supplies exceed their thresholds. Upon power-down, the ADM2483 output signals retain their correct state until at least one of the supplies drops below its power-down threshold. When the VDD1 power-down threshold is crossed, the ADM2483 output signals reach their unpowered states within 4 s. Table 11. Power-Up/Power-Down Thresholds
Supply VDD1 VDD1 VDD2 VDD2 Transition Power-Up Power-Down Power-Up Power-Down Threshold (V) 2.0 1.0 3.3 2.4
- d 2 V = rn ; n = 1, 2, . . . , N dt
where: is the magnetic flux density (Gauss). N is the number of turns in receiving coil. rn is the radius of nth turn in receiving coil (cm). Given the geometry of the receiving coil and an imposed requirement that the induced voltage is not more than 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 27.
Rev. 0 | Page 15 of 20
ADM2483
100 1000
10
MAXIMUM ALLOWABLE CURRENT (kA)
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGAUSS)
DISTANCE = 1m 100 DISTANCE = 5mm 10
1
0.1
DISTANCE = 100mm 1
0.01
04736-027
0.1
04736-028
0.001 1k
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
0.01 1k
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 27. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kGauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurred during a transmitted pulse and was of the worst-case polarity, it would reduce the received pulse from >1.0 V to 0.75 V. This would be well above the 0.5 V sensing threshold of the decoder. As a convenience to the user, these magnetic flux density values are shown in Figure 28, using more familiar quantities such as maximum allowable current flow, at given distances away from the ADM2483 transformers.
Figure 28. Maximum Allowable Current for Various Current-to-ADM2483 Spacings
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce large enough error voltages to trigger the thresholds of succeeding circuitry. To avoid this possibility, be careful in the layout of such traces.
Rev. 0 | Page 16 of 20
ADM2483 APPLICATIONS INFORMATION
POWER_VALID INPUT
To avoid glitches on outputs A and B caused by slow power-up and power-down transients on VDD1 (>100 s/V), the ADM2483 features a power_valid (PV) digital input. This pin should be driven low until VDD1 exceeds 2.0 V. When VDD1 is greater than 2.0 V, the pin should be driven high. Conversely, upon powerdown, the PV should be driven low before VDD1 reaches 2.0 V. The power_valid input can be driven, for example, by the output of a system reset circuit such as the ADM809Z, which has a threshold voltage of 2.32 V.
VDD1
ISOLATED POWER SUPPLY CIRCUIT
The ADM2483 requires isolated power capable of 5 V at 100 mA, to be supplied between VDD2 and GND2 pins. If no suitable integrated power supply is available, then a discrete circuit, such as the one in Figure 25, can be used. A center tapped transformer provides electrical isolation. The primary winding is excited with a pair of square waveforms that are 180 out of phase with each other. A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP667 linear voltage regulator provides a regulated power supply to the ADM2483's bus-side circuitry. To create the pair of square waves, a D-type flip-flop with complementary Q/Q outputs is used. The flip-flop can be connected so that output Q follows the clock input signal. If no local clock signal is available, then a simple digital oscillator may be implemented with a hex inverting Schmitt trigger and resistor and capacitor. In this case, values of 3.9 kV and 1 nF generate a 364 kHz square wave. A pair of discrete NMOS transistors, switched by the Q/Q flip-flop outputs, conduct current through the center tap of the primary transformer winding in an alternating fashion.
04736-029
VDD1
ADM809Z
RESET
ADM2483
PV GND1
VDD1 2.0V
2.32V
2.32V
2.0V
RESET
tPOR
Figure 29. Driving PV with ADM809Z
VCC 3.9k VCC 100nF D
100nF BS107A
ISOLATION BARRIER SD103C IN OUT VCC BS107A 78253 SD103C VCC VDD1 VDD2 22F 5V
PR
CLR Q
ADP667
SET GND SHDN
74HC74A CLK 74HC14 10nF Q
ADM2483
GND1 GND2
04736-030
Figure 30. Isolated Power Supply Circuit
Rev. 0 | Page 17 of 20
ADM2483 OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
16 9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) x 45 0.25 (0.0098)
SEATING PLANE
8 0.33 (0.0130) 0 0.20 (0.0079)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 31. 16-Lead Standard Small Outline Package [SOIC] Wide Body (RW-16) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADM2483BRW ADM2483BRW-REEL1 Data Rate (kbps) 500 500 Temperature Range -40C to +85C -40C to +85C Package Description 16-Lead Wide Body SOIC 16-Lead Wide Body SOIC Package Option RW-16 RW-16
1
The addition of a -REEL suffix designates a 13-inch (1000 units) tape-and-reel option.
Rev. 0 | Page 18 of 20
ADM2483 NOTES
Rev. 0 | Page 19 of 20
ADM2483 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04736-0-10/04(0)
Rev. 0 | Page 20 of 20

▲Up To Search▲

Price & Availability of ADM2483

	To Download ADM2483 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .